# 参照zcu102-dpu-trd-2019-1-timer/pl/srcs/
# close_project
cd ~/VitisAI/
create_project prj_name Vivado_zcu104 -part xczu7ev-ffvc1156-2-e
# set_property part xczu3eg-sfvc784-2-e [current_project]
set_property board_part xilinx.com:zcu104:part0:1.1 [current_project]
create_bd_design "top"
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0
# DPU库来源: https://github.com/Xilinx/Vitis-AI/，国内镜像https://gitee.com/H712/Vitis-AI
# set_property  ip_repo_paths ~/Downloads/Vitis-AI/DPU-TRD/dpu_ip/dpu_eu_v3_2_0 [current_project]
# set_property  ip_repo_paths f:/FPGA/Vitis-AI/DPU-TRD/dpu_ip/DPUCZDX8G_v3_3_0 [current_project]
set_property  ip_repo_paths /home/user/tools/Vitis-AI_v1.3/dsa/DPU-TRD/dpu_ip/DPUCZDX8G_v3_3_0 [current_project]
update_ip_catalog -rebuild -scan_changes
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dpu
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_axi
# create_bd_cell -type ip -vlnv xilinx.com:ip:dpu_eu:3.2 dpu_eu0
create_bd_cell -type ip -vlnv xilinx.com:ip:DPUCZDX8G:3.3 dpu_eu0
create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynqMP
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_sys
set_property screensize {320 220} [get_bd_cells zynqMP]
set_property location {1 0 230} [get_bd_cells rst_dpu]
set_property location {1 0 400} [get_bd_cells rst_axi]
set_property location {1 0 0} [get_bd_cells dpu_eu0]
set_property location {2 0 30} [get_bd_cells zynqMP]
set_property location {2 0 250} [get_bd_cells rst_sys]
set_property location {2 0 400} [get_bd_cells clk_wiz_0]
apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e -config {apply_board_preset "1" }  [get_bd_cells zynqMP]
# ZynqMP: M_AXI_GP0/1=HPM0/1_FPD, M_AXI_GP2=HPM0_LPD, S_AXI_GP0/1=HPC0/1_FPD, S_AXI_GP2/3/4/5=HP0/1/2/3_FPD, S_AXI_GP6=LPD, DATA_WIDTH=PG338_Table1默认256? ug1085,Figure 15-1,Figure 35-6
set_property -dict [list \
	CONFIG.PSU__USE__M_AXI_GP0 {0} CONFIG.PSU__USE__M_AXI_GP1 {0} \
	CONFIG.PSU__USE__M_AXI_GP2 {1} CONFIG.PSU__MAXIGP2__DATA_WIDTH {32}\
	CONFIG.PSU__USE__S_AXI_GP0 {0} CONFIG.PSU__USE__S_AXI_GP1 {0} \
	CONFIG.PSU__USE__S_AXI_GP2 {1} CONFIG.PSU__SAXIGP2__DATA_WIDTH {128}\
	CONFIG.PSU__USE__S_AXI_GP3 {1} CONFIG.PSU__SAXIGP3__DATA_WIDTH {128}\
	CONFIG.PSU__USE__S_AXI_GP4 {1} CONFIG.PSU__SAXIGP4__DATA_WIDTH {32}\
	CONFIG.PSU__USE__S_AXI_GP5 {0} CONFIG.PSU__USE__S_AXI_GP6 {0} \
	CONFIG.PSU__USE__IRQ0 {1} CONFIG.PSU__USE__IRQ1 {0}
] [get_bd_cells zynqMP]
# DPU: Arch=B4096×1, SFM=Disable, dpu_2x=Enable
set_property -dict [list CONFIG.CLK_GATING_ENA {1} CONFIG.DNNDK_PRINT {Number of DPU Cores:1;Arch of DPU:B4096;RAM Usage:Low;Channel Augmentation:Enabled;DepthWiseConv:Enabled;AveragePool:Enabled;ReLU Type:ReLU + LeakyReLU + ReLU6;Number of SFM cores:0;S-AXI Clock Mode:Independent;dpu_2x Clock Gating:Enabled;DSP48 Maximal Cascade Length:4;DSP48 Usage:High;Ultra-RAM Use per DPU:0;Enable timestamp auto-update:Enabled;Target Version:1.4.1;AXI Protocol:AXI4;S-AXI Data Width:32;M-AXI GP Data Width:32;M-AXI HP Data Width (DPU):128;M-AXI HP Data Width (SFM):128;M-AXI ID Width:2;DSP Slice Count:690;Ultra-RAM Count:0.0;Block-RAM Count:257.0} CONFIG.ARCH {4096}] [get_bd_cells dpu_eu0]
set_property -dict [list \
	CONFIG.PRIMITIVE {Auto} CONFIG.USE_LOCKED {true} CONFIG.USE_RESET {true} CONFIG.CLKOUT2_USED {true} \
	CONFIG.CLK_OUT1_PORT {dpu_2x} CONFIG.CLK_OUT2_PORT {axi_clk} CONFIG.RESET_TYPE {ACTIVE_LOW}\
	CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {650} CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {325} \
	CONFIG.CLKOUT1_DRIVES {Buffer_with_CE} CONFIG.CLKOUT1_MATCHED_ROUTING {true} CONFIG.CLKOUT2_MATCHED_ROUTING {true} \
] [get_bd_cells clk_wiz_0]
connect_bd_net [get_bd_pins zynqMP/pl_clk0] [get_bd_pins zynqMP/maxihpm0_lpd_aclk]
connect_bd_net [get_bd_pins zynqMP/pl_clk0] [get_bd_pins clk_wiz_0/clk_in1]
connect_bd_net [get_bd_pins zynqMP/pl_clk0] [get_bd_pins dpu_eu0/s_axi_aclk]
connect_bd_net [get_bd_pins zynqMP/pl_clk0] [get_bd_pins rst_sys/slowest_sync_clk]
connect_bd_net [get_bd_pins zynqMP/pl_resetn0] [get_bd_pins rst_sys/ext_reset_in]
connect_bd_net [get_bd_pins clk_wiz_0/dpu_2x] [get_bd_pins rst_dpu/slowest_sync_clk]
connect_bd_net [get_bd_pins clk_wiz_0/dpu_2x] [get_bd_pins dpu_eu0/dpu_2x_clk]
# connect_bd_net [get_bd_pins clk_wiz_0/dpu_2x] [get_bd_pins dpu_eu0/dpu1_2x_clk]
connect_bd_net [get_bd_pins clk_wiz_0/axi_clk] [get_bd_pins zynqMP/saxihp0_fpd_aclk]
connect_bd_net [get_bd_pins clk_wiz_0/axi_clk] [get_bd_pins zynqMP/saxihp1_fpd_aclk]
connect_bd_net [get_bd_pins clk_wiz_0/axi_clk] [get_bd_pins zynqMP/saxihp2_fpd_aclk]
connect_bd_net [get_bd_pins clk_wiz_0/axi_clk] [get_bd_pins dpu_eu0/m_axi_dpu_aclk]
connect_bd_net [get_bd_pins clk_wiz_0/axi_clk] [get_bd_pins rst_axi/slowest_sync_clk]
connect_bd_net [get_bd_pins clk_wiz_0/locked] [get_bd_pins rst_dpu/dcm_locked]
connect_bd_net [get_bd_pins clk_wiz_0/locked] [get_bd_pins rst_axi/dcm_locked]
connect_bd_intf_net [get_bd_intf_pins dpu_eu0/S_AXI] [get_bd_intf_pins zynqMP/M_AXI_HPM0_LPD]
connect_bd_intf_net [get_bd_intf_pins dpu_eu0/DPU0_M_AXI_DATA0] [get_bd_intf_pins zynqMP/S_AXI_HP0_FPD]
connect_bd_intf_net [get_bd_intf_pins dpu_eu0/DPU0_M_AXI_DATA1] [get_bd_intf_pins zynqMP/S_AXI_HP1_FPD]
connect_bd_intf_net [get_bd_intf_pins dpu_eu0/DPU0_M_AXI_INSTR] [get_bd_intf_pins zynqMP/S_AXI_HP2_FPD]
# connect_bd_intf_net [get_bd_intf_pins dpu_eu0/SFM_M_AXI] [get_bd_intf_pins zynqMP/S_AXI_HPC0_FPD]
connect_bd_net [get_bd_pins dpu_eu0/dpu_2x_clk_ce] [get_bd_pins clk_wiz_0/dpu_2x_ce]
# connect_bd_net [get_bd_pins dpu_eu0/dpu_2x_clk_ce] [get_bd_pins clk_wiz_0/dpu1_2x_ce]
connect_bd_net [get_bd_pins dpu_eu0/dpu_interrupt] [get_bd_pins zynqMP/pl_ps_irq0]
connect_bd_net [get_bd_pins rst_axi/peripheral_aresetn] [get_bd_pins dpu_eu0/m_axi_dpu_aresetn]
connect_bd_net [get_bd_pins rst_sys/peripheral_aresetn] [get_bd_pins clk_wiz_0/resetn]
connect_bd_net [get_bd_pins rst_sys/peripheral_aresetn] [get_bd_pins rst_axi/ext_reset_in]
connect_bd_net [get_bd_pins rst_sys/peripheral_aresetn] [get_bd_pins rst_dpu/ext_reset_in]
connect_bd_net [get_bd_pins rst_sys/peripheral_aresetn] [get_bd_pins dpu_eu0/s_axi_aresetn]
connect_bd_net [get_bd_pins rst_dpu/peripheral_aresetn] [get_bd_pins dpu_eu0/dpu_2x_resetn]
assign_bd_address
make_wrapper -files [get_files Vivado_zcu104/prj_name.srcs/sources_1/bd/top/top.bd] -top
add_files -norecurse Vivado_zcu104/prj_name.srcs/sources_1/bd/top/hdl/top_wrapper.v
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 8
# 需要运行完毕后运行
write_hw_platform -fixed -force -include_bit -file Vivado_zcu104/zcu104.xsa